Integration of semiconductor lasers to planar optical components, such as waveguides, semiconductor optical amplifiers (SOAs) and detectors, is important for integrated circuit applications. When working with photonic integrated circuits it is essential to control reflections from the interfaces between integrated photonic components. With proper design, interface reflections may be used to enhance performance of integrated lasers.
One method is to precisely space gaps between components to coherently enhance or reduce reflections from the interfaces. Prior art methods describe the use of resonant and anti-resonant etched gaps used to couple between lasers, SOAs and other lasers, taking advantage of the index discontinuity across air gaps to selectively enhance or reduce reflections across interfaces. A similar process has been demonstrated to create semiconductor lasers that make use of etched gaps in the semiconductor material to enhance reflectivity of the laser mirrors. At near-infrared wavelengths, electron beam lithography is frequently required to provide the necessary resolution to define the etch masks used to create the resonant gaps.
“A Sub-Micron Capacitive Gap Process for Multiple-Metal-Electrode Lateral Micromechanical Resonators,” Wan That Hsu, et al, Technical Digest, 14th International IEEE Micro Electro Mechanical Conference, January 2001, discloses a process for fabricating a semiconductor having gaps between metal electrodes and a polysilicon resonator resident on the semiconductor. With this method, a sacrificial spacer layer is deposited on a substrate. A polysilicon resonator is then deposited and etched over the sacrificial layer, during which time portions of the sacrificial layer are removed, and the metal electrodes are formed through electroplating on either side of the resonator. The sacrificial layer is ultimately removed in its entirety. The present invention does not operate in the same manner as this process. The Hsu article is hereby incorporated by reference into the present invention.
“12 μm long edge-emitting quantum-dot laser,” S. Rennon, et al, Electronics Letters, May 2001, discloses a series of mirrors and a central waveguide. Each of the mirrors and the central waveguide are etched. Bragg mirrors are patterned by electron-beam lithography on the rear side of the waveguide with air gaps etched between the Bragg gratings. First order mirrors are etched on the front side of the waveguide. The air gaps between Bragg mirrors decrease reflection loss in the laser produced by this method. The present invention is not fabricated in the same manner as the invention of Rennon, et al. Rennon, et al is hereby incorporated by reference into the specification of the present invention.
“Air Trench Bends and Splitters for Dense Optical Integration in Low Index Contrast,” Shoji Akiyama, et al, Journal of Lightwave Technology, July 2005, discloses air trench waveguides, and specifically air trench bend structures. It specifically describes a process for creating a waveguide with air trenches by first patterning the waveguide through a dry etching process and thereafter patterning the air trenches through a photolithography and dry etching process. The process of the present invention does not operate in this manner. Akiyama, et al is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 6,917,109, entitled “AIR GAP STRUCTURE AND FORMATION METHOD FOR REDUCING UNDESIRED CAPACITIVE COUPLING BETWEEN INTERCONNECTS IN AN INTEGRATED CIRCUIT DEVICE,” discloses a method for creating air gaps in integrated circuits between patterned interconnect structures. In the method of the invention, interconnect structures are patterned on a semiconductor device with trenches being etched between the interconnect structures. A dielectric layer is then patterned over the device and air gaps are formed in the dielectric layer. The present invention does not operate in the same method as the patent. U.S. Pat. No. 6,917,109 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 6,915,054, entitled “METHODS FOR PRODUCING WAVEGUIDES,” discloses a method for producing waveguides using a sacrificial layer. A waveguide is produced by first depositing a metal layer on a substrate. A sacrificial layer is then deposited over the metal layer and a second metal layer is deposited over the sacrificial layer and contacts the first metal layer. The second metal layer defines a cavity between the first and second layer, the cavity being filled with the sacrificial layer. The sacrificial layer is thereafter removed. The present invention does not operate in the same manner as the method of the patent. U.S. Pat. No. 6,915,054 is hereby incorporated by reference into the present invention.
U.S. patent application Ser. No. 09/412,682, entitled “SACRIFICIAL SPACER FOR INTEGRATED CIRCUIT TRANSISTORS,” discloses a semiconductor integrated circuit with a sacrificial sidewall. Specifically, temporary sidewalls are formed along the side of a gate electrode of a semiconductor. Source/drain regions are then formed on the semiconductor alongside the gate electrode, and the temporary sidewalls are removed, resulting in a space between the gate electrode and the source/drain regions. The present invention does not operate in this manner. U.S. patent application Ser. No. 09/412,682 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 6,486,025, entitled “METHODS FOR FORMING MEMORY CELL STRUCTURES,” discloses two methods for forming memory cell structures in a semiconductor integrated circuit. One method includes the use of a sacrificial spacer layer formed adjacent to the sidewall of a capacitor of a field effect transistor formed on the semiconductor device. A dielectric layer is then formed alongside the spacer layer, through which a bitline stud layer is formed that is electrically connected to the source/drain regions of the field effect transistor. The sacrificial spacer layer is finally removed from the structure. The present invention operates in a different manner from this process. U.S. Pat. No. 6,486,025 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 6,071,805, entitled “AIR GAP FORMATION FOR HIGH SPEED IC PROCESSING,” discloses a method of using a filler material during conventional Damascene processing to form air gaps. After initial construction of the base device, trenches are etched to form metal leads. The trenches are filled with a filler material. A silicon oxide layer is deposited over the metal leads and filler material and vent holes are etched in the silicon oxide material such that each area of filler material is accessed by a vent hole. The filler material is then removed to form air gaps and the final inter-metal oxide layer is deposited on the silicon oxide layer. The present invention does not operate in the same manner as this invention. U.S. Pat. No. 6,071,805 is hereby incorporated by reference into the specification of the present invention.
The methods described above effectively create air gaps and other spaces in semiconductor structures, however the processes are extremely inefficient as applied to optical devices. If it is desirable to create a precise gap structure, such as an air gap or trench, it is common for several processing steps to be used to form both the component and the accompanying gap. This can be both time-consuming and costly. What is desirable in the art is to create an efficient, inexpensive method of creating optical semiconductor devices with integrated gaps.